Top and important Advanced Computer Architecture MCQs with answers are given in this blog post. These multiple-choice questions on advanced computer architecture are important for college exams, university exams, banking and other competitive exams.
Advanced Computer Architecture MCQs with answers
1. Assemblers are programs that convert programs written in ________ to ________.
machine code (0s and 1s), low-level languages
high-level languages, low-level languages
high-level languages, machine code (0s and 1s)
low-level languages, machine code (0s and 1s)
2. What will be the value of r3 after executing the following piece of assembly code?
mov r0, 101
lsl r1, r0, 1
lsl r2, r0, 2
add r3, r1, r2
404
202
101
606
3. Consider the following piece of assembly code executing on a 5-stage in-order pipelined processor.
1) ld r1, 8[r2]
2) st r1, 8[r3]
Which of the following forwarding paths will be used to remove stalls?
RW→ MA
RW→EX
RW→OF
MA→OF
4. Consider a basic processor having five stages. ____ stage sends the branch target of a branch instruction to the fetch stage.
Decode and Operand Fetch (OF)
Execute (EX)
Memory Access (MA)
Register Write-back (RW)
5. Consider the following snippet of code executing on a 5-stage pipeline with forwarding:
1) ld r1, 0[r2]
2) add r3, r1, r4
Which hazard will cause stalls in this execution? Choose the most appropriate answer.
Control hazard
Read After Write (RAW)
Write After Read (WAR)
Load-use hazard
6. Which of the following factors does the number of instructions per cycle (IPC) depend on?
1) The architecture
2) The compiler
3) Transistor technology
4) Latch delay
1 and 2
2 and 3
1,3 and 4
3 and 4
7. Which of the following factors limits the increase in frequency while increasing the number of pipeline stages?
Power and temperature
Latch delay
Number of stalled cycles
All of these
8. The _______ brings two instructions before the branch (which are on the correct path) and places them in the delay slots to avoid control hazards.
Compiler
Assembler
Operating system
Instruction Set Architecture
9. Which of the following limits the size of the instruction window? Choose the most appropriate answer.
The compiler
Number of architectural registers
The accuracy of the branch predictor
Hazards
10. Find the probability of making at least a single mistake (branch misprediction) in a pool of 100 instructions having 25 branches. Given probability of predicting any given branch incorrectly is 0.005.
11.7 %
9.28 %
10%
12.8 %
11. Which kind of data dependence is present in the following code snippet? Choose the most appropriate answer.
mov r1,1
add r3, r1, r2
add r2, r4, r5
True dependence only
Output dependence only
True and anti-dependence only
Output and anti-dependence only
12. What will happen if the number of physical registers in an out-of-order processor increases, keeping the rest of the system unchanged?
The number of assembly instructions per program will increase.
The number of assembly instructions per program will decrease.
The number of assembly instructions per program will stay the same.
Instruction level parallelism will decrease.
13. Consider the statements:
S1: An in-order processor can have imprecise exceptions.
S2: An out-of-order processor always has imprecise exceptions.
Both S1 and S2 are true
S1 is true, but S2 is false
S1 is false, S2 is true
S1 and S2 are both false
14. For a 32-bit PC address, why cannot we have an Instruction Status Table (IST) containing 232 entries (choose the most appropriate answer)?
Destructive interference will be very high.
There will be a lot of branch aliasing.
The IST will not be able to exploit temporal locality.
The IST will require a lot of chip area and power.
15. Let the latest instruction (in program order) to write back its results to either the memory or the register file be instruction I. Which of the following statements must be true to ensure the correctness of the execution:
S1: All the instructions before I in program order need to complete before the interrupt/exception handler begins to execute.
S2: No instruction after I in program order should have completed at this point.
Both S1 and S2 are true
S1 is true, but S2 is false
S1 is false, S2 is true
S1 and S2 are both false
16. Which of the following statements about register renaming are true?
S1: Renaming in hardware is preferred over renaming by the compiler.
S2: Renaming removes all dependencies.
Only S1 is true
Only S2 is true
Both the statements are false
Both the statements are true.
17. Consider a GAg predictor in which the Branch History Register has 16 entries, and each entry in the Pattern history table (PHT) is a 2-bit saturating counter. What is the size of the PHT (in bits)?
32768
2048
65536
131072
18. What would be the misprediction rate of a simple bimodal predictor if the default outcome is “not taken”?
1/6
2/7
2/5
1/8
19. Which of the following hardware structures is used for predicting whether a given instruction is a branch or not? Choose the most appropriate answer.
BTB
BHR
PHT
Saturating counter
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