Another set of Computer Organization and architecture MCQ is provided in this post. In the previous set, we provided 19 multiple choice questions on Advanced Computer Architecture MCQs.
Set 1: Advanced Computer Architecture MCQs
Set 2: Computer organization and architecture MCQ with answers
1. Which of the following pieces of information does the instruction packet include? Choose the most appropriate answer.
1) opcode (type)
2) ids of source registers
3) constants and offsets
4) control signals
1 and 4
2 and 3
1, 2, 3 and 4
1 and 2
2. Which instructions are typically very hard to decode?
Complex Instruction Set Computer (CISC) instructions
Reduced Instruction Set Computer (RISC) instructions
Minimal Instruction Set Computer (MISC) instructions
None of these
3. To ensure precise exceptions, the architectural registers should appear to be updated _____.
out of order
sequentially
in-order
parallelly
4. ____ is the number of physical registers, ____ is the number of instructions that can simultaneously be in flight; ____ is the ILP.
More, higher, less
More, higher, more
Less, lower, more
Less, higher, less
5. Consider the following statements:
S1: The free list is a queue of mapped physical register file ids.
S2: The Dependence Check Logic (DCL) takes care of dependencies between instructions renamed in the same cycle.
Only S1 is true
Only S2 is true
Both S1 and S2 are true
Both S1 and S2 are false
6. Consider the following statements:
S1: The number of instructions per cycle ‘w’ to be sent to the execution units is known as the issue width.
S2: The instruction window buffers instructions till they are consumed and thus tries to reduce the mismatch between the rate of production and the rate of consumption.
Only S1 is true
Only S2 is true
Both S1 and S2 are true
Both S1 and S2 are false
7. Once an instruction sees the tag on a tag bus, the operand is deemed to be ____. Once all the operands are ready, the instruction _____ , and is ready to_____.
Waiting, waits, fetch
Waiting, wakes up, dispatch
Ready, wakes up, execute
Ready, waits, execute
8. Consider the following statements:
S1: The dispatch unit chooses one instruction among several ready instructions.
S2: The select policy has an important implication on performance. We should select those instructions that are the most performance-critical.
Only S1 is true
Only S2 is true
Both S1 and S2 are true
Both S1 and S2 are false
9. A producer instruction can let all its consumer instructions know that the value of its destination register is ready through the _____ mechanism.
Forwarding
Broadcast
Wakeup
Select
10. Which of the following is not present in the context of a program?
Values of all the architectural registers
Contents of the memory
Program counter of the next instruction to execute
Values of all the pipeline registers
11. What happens when there are no free entries in the Reorder Buffer?
The entire out-of-order pipeline stalls
Only fetch and decode stages stall
Only execution stage stalls
None of the choices
12. Consider the statements about CAM (Content Addressable Memory):
S1: Elements stored in a CAM-based storage structure are usually addressed using an index.
S2: CAM-based storage structures are slower than index-based storage structures.
Both S1 and S2 are true
S1 is true, but S2 is false
S1 is false, S2 is true
S1 and S2 are both false
13. In load-store dependence prediction, what does the store set corresponding to every load contain?
Set of stores that have forwarded a value to the given load in the recent past.
Set of loads that have been forwarded a value from some store in the recent past.
List of stores that are yet to forward a value
None of the choices
14. Consider the following statements regarding the free list:
S1: It is a software structure that maintains a list of physical registers that are currently free and can be assigned to architectural registers.
S2: The free list is typically implemented as a circular queue.
Both S1 and S2 are true
S1 is true, but S2 is false
S1 is false, S2 is true
S1 and S2 are both false
15. Which entries of the ROB are discarded if there is branch misprediction?
All entries in the ROB that are before the mispredicted branch instruction
Entries in the ROB that are after the mispredicted branch instruction
The entire ROB is flushed
The forward slice is flushed
16. What is the value of the minimum number of iterations required to identify a stride-based access pattern?
1
3
0
2
17. When do we need to do register spilling?
When the number of live variables during the execution of a program is more than the number of available registers
When the number of available registers during the execution of a program is more than the number of live variables
When the cache memory is full
When the pipeline stalls
Thanks for reading Computer organization and architecture MCQ on our website. This is Set 2.
Set 1: Advanced Computer Architecture MCQs